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Technical Overview of the Semiconductor Chip Industry
Precio para miembros
$625.00
Nonmember Price
$850.00
Acceso
90 Días a partir de la Inscripción
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Nivel del Curso: Introducción
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Tiempo del Curso
3 weeks (6 two-hour online instructor-led sessions) -
Certificado Obtenido
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Seasonal Enrollment
Acceso durante 90 Días
All virtual class sessions are recorded and available for review.
WEEK 1: Lecture 1
- Introduction to Semiconductor Basics (Microelectronics)
- Semiconductor materials, P-N Junctions
- Bipolar Junction Transistor, CMOS transistor technologies
- VMOS, DMOS, BCD, FinFET, and GAA Technologies
- IC packaging types and evolution
- Semiconductor Supply Chain and Global Relationships
- Integrated device manufacturer (IDM), fabless, design house, outsourced assembly, and testing (OSAT) and IP (blocks or cell library)
- Semiconductor cycle
- International Roadmap for Devices and Systems (IRDS)
- Semiconductor Industry Association (SIA)
- Challenges in the industry
Weel 1: Lecture 2
- IC Design Process 1 (Front-end)
- The general flow of IC design
- Specifications of a chip
- Electronic design automation (EDA or CAD)
- Basic digital design flow
- Process development kit (PDK)
- Design entry: HDL or Verilog language
- IC Design Process 2 (Front-end)
- Basic analog IC design flow
- Specification of a chip
- Schematic entry & simulation
- Floor plan concepts
- Primitive cells (PCells, with examples)
- Cross-sectional view (with examples)
- Layout (mask) design
ASSIGNMENT: Revision of terminologies and concepts (Puzzle 1)
WEEK 2: Lecture 3
- Facilities and Raw Material
- Cleanroom classification
- General safety
- Electrostatic Discharge (ESD)
- Wafer preparation (raw material – ingot)
- Wafer size
- Wafer Fabrication Processes (Basic) Part 1
- Process flow chart (simplified)
- Oxidation:
- Dry
- Wet
- Lithography:
- Imaging
- Mask, reticle
- Photoresist (PR)
- Etching:
- Dry
- Wet
Week 2: Lecture 4
- Wafer Fabrication Processes (Basic) Part 2
- Ion implantation
- Diffusion
- Annealing (rapid thermal process [RTP])
- Deposition:
- Chemical vapor deposition (CVD)
- Physical vapor deposition (PVD) (Sputtering)
- Low Pressure (LPVD)
- Plasma Enhanced (PECVD)
- Wafer Fabrication Processes (Basic) Part 3
- Chemical mechanical polishing (CMP)
- Metallization
- Passivation
- Metrology (Measurement)
- Wafer sort (Mapping)
- Yield
ASSIGNMENT: Revision of terminologies and concepts (Puzzle 2)
WEEK 3: Lecture 5
- Backend Semiconductor Assembly and Test 1
- Review of outsource assembly and testing (OSAT) operations
- IC packaging and evolution
- Dicing (Sawing)
- Die attach
- Wire bond or flip chip
- Encapsulation (molding)
- Marking
- Backend Semiconductor Assembly and Test 2
- General flow of IC testing
- IC test equipment and setup
- Wafer test and IC package test
- Types of tests
- Review of electrical test
- DC, AC, functional test
- Build-in-self-test (BIST)
- JTAG Boundary Scan
- Burn-in test
Week 3: Lecture 6
- Introduction to Chip Package Failure Analysis
- Bathtub curve (reliability)
- What and why failure analysis
- Failure modes
- Investigation flow
- Non-destructive / destructive
- Visual inspection example
- Example of a full flow (open circuit)
- Final Exam Review
ASSIGNMENT: Final Exam
You must achieve a final exam score of 70% or higher to earn a certificate of completion. You are allowed two attempts, and the highest grade is recorded.
Everyone is welcome, even those with little or no knowledge of the subject, because the content is presented in a clear and accessible way.
PC offers different instructional modalities to suit participants with different needs and preferences. This program is only available in the following modality:
Online-instructor-led: Participants go online to meet with an IPC-certified industry expert at a fixed time twice per week for the duration of the course. Class sessions are usually 1.5 to 2 hours. Participants can also access a video recording of each class session on their IPC EDGE course dashboard.
Cheah Soo Lan, is an engineering manager with more than 30 years of experience in the electronics and semiconductor industry. She’s proficient with both PCB CAD and custom IC design layout tools and is a certified Master IPC Trainer for PCB Design CID and CID+ under IPC Asia. Cheah Soo Lan spent the last 15 years as a manager in technical and vocational education for Malaysia. Prior to teaching, she worked 15 years as an engineer in support of network and television, research, and development of electronic and semiconductors at the national research centers and defense industry of Singapore.